COMP 2611 Homework 4

Q1

a

Iteration	Multiplicand (M)	Product (P)	Action
0	0011 0101	0000 0000 1100 1010	Initial state
1	0011 0101	0000 0000 1100 1010	No operation
		0000 0000 0110 0101	Shift right
2	0011 0101	0011 0101 0110 0101	Addition
		0001 1010 1011 0010	Shift right
3	0011 0101	0001 1010 1011 0010	No operation
		0000 1101 0101 1001	Shift right
4	0011 0101	0100 0010 0101 1001	Addition
		0010 0001 0010 1100	Shift right
5	0011 0101	0010 0001 0010 1100	No operation
		0001 0000 1001 0110	Shift right
6	0011 0101	0001 0000 1001 0110	No operation
		0000 1000 0100 1011	Shift right
7	0011 0101	0011 1101 0100 1011	Addition
		0001 1110 1010 0101	Shift right
8	0011 0101	0101 0011 1010 0101	Addition
		0010 1001 1101 0010	Shift right

b

Overflow, because the higher 8 bits are not all 0

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Q2

a

Iteration	Divisor (D)	Remainder (R)	Action
0	0001 1001	0000 0000 0110 1000	Initial state
		0000 0000 1101 0000	Shift left
1	0001 1001	1110 0111 1101 0000	Subtraction
		0000 0000 1101 0000	Undo
		0000 0001 1010 0000	Shift left, set LSb 0
2	0001 1001	1110 1000 1010 0000	Subtraction
		0000 0001 1010 0000	Undo
		0000 0011 0100 0000	Shift left, set Lsb 0
3	0001 1001	1110 1010 0100 0000	Subtraction
		0000 0011 0100 0000	Undo
		0000 0110 1000 0000	Shift left, set Lsb 0
4	0001 1001	1110 1101 1000 0000	Subtraction
		0000 0110 1000 0000	Undo
		0000 1101 0000 0000	Shift left, set Lsb 0
5	0001 1001	1111 0100 0000 0000	Subtraction
		0000 1101 0000 0000	Undo
		0001 1010 0000 0000	Shift left, set Lsb 0
6	0001 1001	0000 0001 0000 0000	Subtraction
		0000 0010 0000 0001	Shift left, set Lsb 1
7	0001 1001	1110 1001 0000 0001	Subtraction
		0000 0010 0000 0001	Undo
		0000 0100 0000 0010	Shift left, set Lsb 0
8	0001 1001	1110 1011 0000 0010	Subtraction
		0000 0100 0000 0010	Undo
		0000 1000 0000 0100	Shift left, set Lsb 0
9	0001 1001	0000 0100 0000 0100	Adjust remainder

The quotient is 0000 0100
The remainder is 0000 0100

b

Since dividend is negative and divisor is positive, quotient and remainder will be both negative

negate quotient: 0000 0101 → 1111 1010 → 1111 1011
negate remainder: 0000 1011 → 1111 0100 → 1111 0101

The quotient is 1111 1011
The remainder is 1111 0101

Q3

a

Little endian: 0x 04 00 A9 AE
Big endian: 0x AE A9 00 04
Binary: 1010 1110 1010 1001 0000 0000 0000 0100

b

101011 10101 01001 0000000000000100

opcode: 101011 → 0x2B → sw (I type instruction)
rs: 10101 → 0x15 → 0d21 → $s5rt:01001->0x9->0d9->$t1
immediate: 0000000000000100 → 0x04 → 0d4

sw $t1, 4($s5)

c

A: 10101
B: 01001
C: Undetermined
D: 0001 0000 0000 0001 0000 0000 0100 0000 (0x10010040)
E: 0000 0000 0000 0000 0001 0000 0000 0001 (0x00001001)
F: 0000 0000 0000 0000 0000 0000 0000 0100

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d

D: 0b 0001 0000 0000 0001 0000 0000 0100 0000
F: 0b 0000 0000 0000 0000 0000 0000 0000 0100
+
G: 0b 0001 0000 0000 0001 0000 0000 0100 0100

G = D + F
G: 0001 0000 0000 0001 0000 0000 0100 0100 (0x10010044)

e

Address	Content
0x10010040	0x20
0x10010041	0x24
0x10010042	0x04
0x10010043	0x01
0x10010044	0x01
0x10010045	0x10
0x10010046	0x00
0x10010047	0x00

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Q4

a

• For the outputs of ALU
  • ALUresults[31] is asserted if subtraction result is negative
  • Zero is asserted if subtraction results in zero
• If either one of the above output is asserted, the input is less than or equal to zero, this is checked by the added OR gate
• If the above condition is true, we check if blez is asserted with the added AND gate, and it would output the result to the final OR gate
• Depending on the result of the previous AND gate, the MUX will receive an asserted input if blez is asserted and the input is actually less than or equal zero, and the branching target will be obtained from the sum of the sign extended lower 16 bits multiplied by 4 and PC + 4, which will finally be updated/stored to PC

b

Instr	RegDst	ALUSrc	Mem toReg	Reg Write	Mem Read	Mem Write	Branch	blez	ALU control
blez	x	0	x	0	0	0	0	1	0110